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| iru3072 1 rev. 1.03/25/04 www.irf.com descriptionthe iru3072 controller ic is designed to provide a low cost synchronous buck regulator for on-board dc to dc converter for multi-output applications. the outputs can be programmed as low as 0.8v for low voltage applica- tions. the iru3072 features dual soft-starts which allows power sequencing between outputs. over current limit is provided by using external mosfet's on-resistance for optimum cost and performance. this device features a programmable frequency set from 200khz to 400khz, under-voltage lockout for all input supplies, dual external programmable soft-start functions as well as output under-voltage detection that latches off the device when an output short is detected. synchronous controller plus 3-ldo controllerscurrent limit using mosfet sensing dual soft-start function allows power sequencing single 5v/12v supply operation programmable switching frequency up to 400khz fixed frequency voltage mode 1a peak output drive capability package order information features 20-pin synchronous pwm controller/ 3 ldo controller applications graphic cardddr memory source sink v tt application applications with multiple outputslow cost on-board dc to dc such as 5v to 3.3v, 2.5v or 1.8v hard disk drive t a (c) device package 0 to 70 iru3072ch 20-pin mlpq 4x4 (h) data sheet no. pd94698 figure 1 - typical application of iru3072. typical application iru3072 u1 vcc vc hdrv ldrv fb1 gnd comp ss1 v out1 1.2v @ 8a rt ocset pgnd drv4 fb4 drv3 fb3 drv2 fb2 v sen33 / sdb ssldo 3.3v v out2 2.5v v out3 1.8v v out4 1.5v q1 q2 c210uf q3 c410uf c910uf c130.1uf c14 33nf c1115nf c72x 47uf,16v c8 10uf c123x 330uf, 40m v 6tpb330m, poscap 1uh 1uh q4irf7460 q5irf7460 2.15k r21k 1.25k r41k 866 v r6 1k 3.3k 46.4k r7 vccldo v in =12v c51uf c11uf c60.1uf 6.81k c10 220pf +5v c31uf r1 r3 r5 r9 r8 l2 l1 d1 r10499 v r111k downloaded from: http:///
2 rev. 1.0 3/25/04 iru3072 www.irf.com absolute maximum ratingsvcc and vccldo supply voltage .............................. 25v vc supply voltage .................................................... 25v storage temperature range ...................................... -65c to 150c operating junction temperature range ..................... 0c to 125c caution: for all pins, voltage should not be below -0.5v. caution: stresses above those listed in "absolute maximum ratings" may cause permanent damage to the device. parameter sym test condition min typ max units feedback voltagefeedback voltage fb voltage line regulation uvlo uvlo threshold - vcc uvlo hysteresis - vcc uvlo threshold - vc uvlo hysteresis - vc uvlo threshold - vccldo uvlo hysteresis - vccldo uvlo threshold - v sen33 uvlo hysteresis - v sen33 uvlo threshold - fb1, 2, 3, 4uvlo hysteresis - fb1, 2, 3, 4 supply current vcc dynamic supply current vc dynamic supply current vcc static supply current vc static supply current 5 4 rev. 1.0 3/25/04 iru3072 www.irf.com this pin is connected to a voltage that must be at least 4v higher than the bus voltage ofthe switcher (assuming 5v threshold mosfet) and powers the high side output driver. a minimum of 1 m f, high frequency capacitor must be connected from this pin to ground to provide peak drive current capability.this pin is connected to the drain of the synchronous mosfet and it provides the posi- tive sensing for the internal current sensing circuitry. an external resistor programs the current sense (cs) threshold depending on the r ds of the power mosfet. this pin is used to monitor the 3.3v rail. this pin can be pulled-low to shutdown theoutputs. this pin sets the switching frequency with a resistor to gnd. this pin is connected directly to the output of the switching regulator via resistor divider to provide feedback to the error amplifier. compensation pin of the error amplifier. an external resistor and capacitor network is typically connected from this pin to ground to provide loop compensation. this pin provides soft-start for the switching regulator. an internal current source charges an external capacitor that is connected from this pin to ground which ramps up the output of the switching regulator, preventing it from overshooting as well as limiting the input current. this pin provides soft-start for the ldo controllers. an internal current source charges an external capacitor that is connected from this pin to ground which ramps up the output of the ldo controller, preventing it from overshooting as well as limiting the input current. these pins provide feedback for the linear regulator controllers. pin# pin symbol pin description 1011 12 13 14 15 16 17 18 19 20 vc ocset v sen33 /sdb rt fb1 comp ss1 ss ldo fb2fb3 fb4 downloaded from: http:/// iru3072 5 rev. 1.03/25/04 www.irf.com block diagram figure 2 - simplified block diagram of the iru3072. 20ua 64uamax por oscillator error amp ct error comp 64ua 3 25k=1.6v when ss=0 reset dom por 0.4v fblo comp vc hdrv vcc ldrv pgnd ss1 fb1 comp 25k 3v r s q rt gnd rt cs comp ocset 3v 20ua 20ua 64uamax ss ldo 0.8v v sen33 / sdb drv2 drv3 drv4 0.8v vccldo fb2 fb3 fb4 bias generator 0.8v 3v por vccldo uvlo 2.5v / 2.35v 1.27v / 1.2v vc 3.5v / 3.3v vcc 4.2v / 4.0v enbl 12 17 16 15 14 11 4 18 19 20 1 2 3 7 8 6 5 9 10 13 64uamax 64uamax 25k 25k 25k 25k 1.27v downloaded from: http:/// 6 rev. 1.0 3/25/04 iru3072 www.irf.com typical application figure 3 - typical application of iru3072. ref desig description value qty part# manuf web site (www.) 32 1 1 1 1 2 3 1 2 2 1 1 1 3 1 1 3 1 1 1 1 1 1 1 q1,q2,q3q4,q5 u1 d1 l1 l2 c1,c3 c2,c4,c9 c5 c6,c13 c7 c8 c10 c11 c12 c14 r1 r2,r4,r6 r3 r5 r7 r8 r9 r10 r11 mosfetmosfet controller schottky diode inductor inductor capacitor capacitor capacitor capacitor capacitor capacitor capacitor capacitor capacitor capacitor resistor resistor resistor resistor resistor resistor resistor resistor resistor irlr2703irf7460 iru3072 bat54s ds1608c-102 do3316p-102hc ecj-2vf1c105z ecj-3yb1e105k ecj-2vf1e104z 16tpb47m ecu-v1h221kb ecj-2vb1h153k 6tpb330m ecj-2vb1h333k irir ir ir coilcraft coilcraft panasonic panasonic panasonic sanyo any panasonic panasonic sanyo panasonic any any any any any any any any any irf.comcoilcraft.com maco.panasonic.co.jp sanyo.com maco.panasonic.co.jp sanyo.com maco.panasonic.co.jp 30v, 65m v , 22a 20v, 10m v , 12a synchronous pwm0.2a, 30v 1 m h, 2a 1 m h 1 m f, y5v, 16v 10 m f 1 m f, x7r, 25v 0.1 m f, y5v, 25v 47 m f, 16v 10 m f 220pf, x7r15nf 330 m f, 6.3v, 40m v 33nf, x7r2.15k, 1% 1k, 1% 1.25k, 1% 866 v , 1% 6.81k, 1%3.3k, 1% 46.4k, 1% 499 v , 1% 1k, 1% parts list iru3072 u1 vcc vc hdrv ldrv fb1 gnd comp ss1 v out1 1.2v @ 8a rt ocset pgnd drv4 fb4 drv3 fb3 drv2 fb2 v sen33 / sdb ssldo 3.3v v out2 2.5v v out3 1.8v v out4 1.5v q1 q2 c210uf q3 c410uf c910uf c130.1uf c14 33nf c1115nf c72x 47uf,16v c8 10uf c123x 330uf, 40m v 6tpb330m, poscap 1uh 1uh q4irf7460 q5irf7460 2.15k r2 1k 1.25k r4 1k 866 v r6 1k 3.3k 46.4k r7 vccldo v in =12v c51uf c11uf c60.1uf 6.81k c10 220pf +5v c31uf r1 r3 r5 r9 r8 l2 l1 d1 r10499 v r111k downloaded from: http:/// iru3072 7 rev. 1.03/25/04 www.irf.com the iru3072 controller ic is designed to provide a lowcost synchronous buck regulator for on-board dc to dc converter as well as three linear regulator controllers. it is specially designed for multiple output applications. the outputs can be programmed as low as 0.8v. the iru3072 provides two separate soft-starts. it not only allows different output power sequences, but also allows shutdown of ldo and pwm output regulators individually. the iru3072 provides cycle-by-cycle current limit and output feedback under-voltage lockout. power sequence and under-voltage lockout for correct operation, proper power sequence should be ensured. typically, there are four or five input voltages involved. the power sequence should be proper such that soft- start capacitors (for both ldo and pwm) start to be linearly charged up right after the above five voltages enter into steady state, as shown in the following figure. figure 4 - desired power sequence. vcc: ic biasing voltage.v sen33 : ldo input voltage, for example 3.3v vccldo: input biasing voltage for iru3072 internalldo controller. v bus : input voltage for synchronous buck converter. vc: input biasing voltage for iru3072 internal highside mosfet drivers. v bus = vcc = 5v vc = vccldo created by charge pumpv sen33 = 3.3v application information the iru3072 senses four voltages with under-voltagelockout (uvlo) block. the voltages vcc, vc and vccldo are sensed through the uvlo block. the ldo input volt- age can be sensed through pin v sen33 . although syn- chronous bus voltage (v bus ) is not sensed, in practical, it can be sensed indirectly. typically, only two or threeinput voltages are available. some of the five input volt- ages have to either share or be generated by another method such as charge pump. one example of iru3072 application with only two input voltages, 5v and 3.3v, is shown in figure 5. in this example: the iru3072 will sense all four voltages to ensure all these voltages enter into steady state before the soft- start capacitor is charged up. the operation waveforms are shown in figure 6. figure 5 - iru3072 application with only two power inputs: 5v and 3.3v. input voltage v cc ,v cc ldo, v bus ,vc, etc uvlo threshold voltage soft-start voltage for pwm v ss soft-start voltage for ldo v ss ldo iru3072 u1 vcc vc hdrv ldrv v out1 ocset v sen33 / sdb c6 c10 l1 q4 q5 r7 vccldo v bus =5v uvlo 3.3v drv2 fb2 soft-start ss1 ss ldo l2 downloaded from: http:/// 8 rev. 1.0 3/25/04 iru3072 www.irf.com figure 6 - power sequence. if there are three input voltage sources available, suchas 3.3v, 5v and 12v, the possible connections to en- sure proper operation are shown in the following table. table: possible combination of input voltage source connections to ensure proper start-up operation. (cp refers to charge pump) there are many possible combinations of input voltagesource connections and the table above lists only a few of them. most importantly for a proper power sequence, the soft-start capacitor has to be charged up after all the input voltage sources are established. soft-start one of the useful features of iru3072 is that it allows different start-up times for pwm output and ldo output by programming two separate soft-start capacitors. fig- ure 7 just shows the soft-start for pwm section. 64 m a 3 25k v = 1.6v option 12 3 4 more vcc 5v5v 12v12v v bus 5v 12v12v 5v vc 12v cpcp 12v vccldo 12v12v 12v 12v ldo input 3.3v3.3v 3.3v 3.3v the soft-start operation can ensure the output voltageramps up to the regulated voltage without surge of the current. the iru3072 also has an output feedback uvlo block, which will turn off both high side and low side mosfet driver when the voltage at pin fb1,fb2,fb3 or fb4 is below 0.4v. the feedback uvlo is used to pro- tect the system when the output is in short circuit. how- ever, during the power on of the buck converter, the out- put of buck converter starts from zero and the voltage at pin fb1 will be below 0.4v. the feedback uvlo should be disabled when soft-start capacitor voltage ramps up and down. this is achieved by injecting a current into the fb1 pin (also fb2, fb3 and fb4) during the soft-start and the magnitude of this current is inversely propor- tional to the voltage at soft-start pin (ss or ssldo). the diagram is shown in figure 7 and operation waveforms are shown in figure 8. the operation principle is as follows: initially, the buck converter?s output voltage and the volt- age at pin fb1 are both zero. the voltage at soft-start pin ?ss? is almost zero and about 64 m a current will inject to the pin of fb1 through a 25k v internal resistor. the voltage at the negative input of error amplifier and thepositive input of the feedback uvlo comparator is ap- proximately: figure 7 - iru3072 soft-start diagram. 20ua 64uamax por error amp 64ua 3 25k=1.6v when ss=0 por 0.4v feeback uvlo comp ss1 fb1 comp 25k 0.8v 25k hdrv ldrv 3v downloaded from: http:/// iru3072 9 rev. 1.03/25/04 www.irf.com 32 m a 3 25k v = 0.8v figure 8 - theoretical operation waveforms during soft-start. when the power voltage such as vcc go into steadystate and the output of voltage uvlo ?por? goes high, a 20ua current source charges the external soft-start capacitors. the soft-start voltage ramps up. in the mean time, the current flowing into pin fb1 starts to decrease linearly and so does the voltage at the positive pin of feedback uvlo comparator and the voltage at the nega- tive input of error amplifier. when the soft-start capacitor voltage is around 1v, the current flowing into the fb1 pin is approximately 32 m a. the voltage at the positive input of the error amplifier is approximately:the error amplifier will start to operate and the output voltage starts to increase. as the soft-start capacitor voltage continues to go up, the current flowing into the fb1 pin will keep decreasing. because the voltage at pin of error amplier is regulated to reference voltage 0.8v, the voltage at the fb1 pin is: the feedback voltage increases linearly as the injecting current goes down. the injecting current drops to zero when soft-start voltage is around 2v and the output volt- age goes into steady state. figure 8 shows that the voltage at the positive pin of feedback uvlo comparator is always higher than 0.4v, therefore, feedback uvlo is not functional during soft- start. for pwm: c ss = 0.1 m f, t start @ 5ms for ldos: c ssldo = 33nf, t start @ 2ms v fb1 = 0.8v-25k v3 (injecting current) 20 m a 3 t start /c ss @ 2v-1v c ss @ 20 m a 3 t start /1v ---(1) from the above analysis, the output start up time is theperiod when soft-start capacitor voltage increases from 1v to 2v. the start up time will be dependent on the size of the external soft-start capacitor. the start up time can be estimated by: for a given start up time, the soft-start capacitor can be estimated as: for 5ms start up time, a 0.1 m f soft-start capacitor is required. in practice, the 20 m a current will slightly de- crease as the soft-start voltage goes up. therefore, for a0.1 m f soft-start capacitor, start up time may be slightly longer, e.g. 6ms.the soft-start waveforms are shown in figure 9. in this figure, the start up time for the buck converter v out1 and ldos is different by selecting separate soft-start capaci-tors. figure 9 - soft-start of buck converter (pwm) and ldo. shutdownthe pwm output and ldo output can be turned on and off individually by pulling up and down the correspond- ing soft start capacitors. soft-start voltage voltage at negative input of error amp and feedback uvlo comparator voltage at fb1 pin current flowing into fb1 pin 64ua 0ua 0v 0.8v @ 1.6v 0.8v 0v 3v @ 2v @ 1v output of uvlo por downloaded from: http:/// 10 rev. 1.0 3/25/04 iru3072 www.irf.com (a). shutdown and start up pwm output by controllingsoft start ss1. ldo output such as vout2 will not be affected. (b). shutdown and start up ldo output by controlling soft-start ssldo. pwm output v out1 will not be affected. figure 10 - shutdown pwm or ldo by controlling soft-start. one issue related to shutdown of pwm output by pull-ing down the soft-start, there is a small negative voltage shown in the output during the shutdown. it is because the low side mosfet driver is on when the soft-start capacitor voltage is pulling down. the output inductor resonates with output capacitor and load. this occurs especially often when output current is small (light load or no load condition). the operation waveforms are shown as follows. figure 11 - operation waveforms when pwm converter is shutdown by pulling down the soft-start capacitor. both pwm output and ldo output can be shutdown bypulling the pin v sen33 /sdb down. one example is shown as follows. figure 12 - external shutdown by using pin v sen33 /sdb. iru3072 u1 vcc vc hdrv ldrv v out1 ocset v sen33 / sdb c6 c10 l1 q4 q5 r7 vccldo v bus =5v uvlo 3.3v drv2 fb2 soft-start ss1 ss ldo l2 4.7k external shutdown downloaded from: http:/// iru3072 11 rev. 1.03/25/04 www.irf.com the ldo and pwm output can be shutdown by using atransistor to pull down the pin v sen33 /sdb as shown in figure 12. because the v sen33 /sdb pin also senses the ldo input voltage for the power uvlo block, a high im-pedance resistor such as 4.7k has to be inserted be- tween v sen33 /sdb pin and the input of ldo such as 3.3v. the input voltage uvlo operation will not be affecteddue to the high input impedance nature of v sen33 /sdb pin. the operation waveforms is shown as follows: figure 13 - shutdown by pulling down pin v sen33 /sdb. one feature of shutdown by pulling down v sen33 /sdb is that there is no negative voltage shown in the buck con-verter output because both high side and low side mosfet drivers are off after shutdown. over current protection the iru3072 over current protection is achieved with a cycle-by-cycle current limit and an output voltage under- voltage lockout scheme. the diagram is shown in figure 14. it includes an over current comparator and an output voltage uvlo comparator. the current is sensed through the r ds(on) of the low side mosfet. a resistor, r set , is connected from ocset pin to the drain of the low sidemosfet in order to set the over-current limit. when the low side mosfet q2 is on, the inductor current flows through mosfet q2. the voltage at ocset pin is given as: when voltage v ocset is below zero, the current sensing comparator flips and disables the oscillator. the highside mosfet is turned off and the low side mosfet is on until the inductor currents reduces to below current setting value. the critical inductor current can be calcu- lated by setting: v ocset =20 m a 3 r set -i l 3 r ds(on) v ocset = 20 m a 3 r set -i l 3 r ds(on) = 0 i set = i l (critical) = 20 m a 3 r set /r ds(on) ---(2) t on (normal) @ d 3 t s(nom) = v out /(f s(nom) 3 v in ) figure 14 - iru3072 current limit diagram. the operation is illustrated in figure 15. figure 15 - operation of iru3072 current limit and uvlo. during the normal operation mode, the synchronous buckconverter operates in fixed frequency f s(nom) , which is the normal operation switching frequency and it is deter-mined by the external resistor rt. the output voltage is regulated to the desired voltage and the feedback volt- age is equal to the reference voltage v ref . the turn on time of the high side mosfet is given as: enb oscillator r s q 3v 20ua cs comp err comp 0.4v iru3072 v bus ocset hdrv ldrv fb1 r set q2 q1 l v out rf1 rf2 feedback voltage switching frequency high side mosfet turn on time (t on ) average inductor current i out i out i out i out d max f s(nom) 0.4v v ref =i out normal operation over current limit mode shutdown by uvlo i o(lim) v out f s(nom) 3 v in i o(nom) f s(nom) downloaded from: http:/// 12 rev. 1.0 3/25/04 iru3072 www.irf.com as the load current goes up, the inductor current in-creases and the high side mosfet?s turn on time in- creases a little due to the voltage drop across the high side mosfet r ds(on) . as the output current increases to limit current, i l =i o(lim) , which is set by the resistor r set . the buck converter will go into cycle-by-cycle current limit mode. the operationwaveforms of iru3072 during cycle-by-cycle current mode is shown in figure 16. (a) normal operation.(b). operation at current limit mode. figure 16 - cycle-by-cycle operation when iru3072 is in over-current limit mode. i set = i l(valley) i out = i l(avg) =i l(valley) + d i pk_pk /2 from figure 16, first, the high side mosfet is on for t on period and the inductor current increases during this time.then, the high side mosfet is off and low side mosfet is on. because the inductor current is higher than the critical inductor current i set , the current sensing com- parator goes high and the low side mosfet keeps on.the inductor current is discharged by the output voltage. when the inductor current is below setting current or critical current i set , the current sensing comparator goes low and enables the oscillator. the high side mosfetis turned on again and next cycle starts. the operation frequency is only dependent on the current sensing com- parator and the internal clock frequency is modified by current limit. in conclusion, from figures 15 and 16, two big differ- ences exist between normal operation and current limit mode. first, during current limit mode, the valley induc- tor current is determined by i set . second, in figures 15 and 16, the frequency in currentlimit mode, is lower than normal operation frequency. in general, the output current is represented by: where d i pk_pk is the peak to peak inductor current ripple which is given by: figure 15 shows that the operation frequency of the buckconverter decreases as output current goes up during current limit mode. the on time of high side mosfet is controlled by the output voltage loop so that the voltage at fb pin, still equals the reference voltage, v fb =v ref . the output voltage is regulated to the desired voltage.as a result: where v o(nom) is the nominal output voltage and it is determined by the feedback resistor and reference volt-age as shown in figure 14. the above equation indi- cates that the operation frequency is inversely propor- tional to the output current during the current limit mode. for practical application, the most important is setting up the over current limit threshold. from figure 15, at the current limit threshold i o(lim) , the frequency is still equal to nominal operation frequency. i set =i l(valley) i l(peak) t on t off i l(avg) current limit comparator output inductor current high side mosfet driver hdrv internal clock at current limit internal clock at normal operation d i pk_pk = i l(pk) -i l(valley) = (v in -v out ) 3 t on /l t on = v o(nom) /v in /f s i out(current limit mode) = i set + (v in -v o(nom) ) 3 v o(nom) (2 3 l 3 v in 3 fs) i set i l(peak) d 3 t s(nom) i l(avg) internal clock current limit comparator output inductor current mosfet driver hdrv t s(nom) i l(valley) downloaded from: http:/// iru3072 13 rev. 1.03/25/04 www.irf.com f s = f s(nom) therefore, the output current limit threshhold is set by:where: from equation (2), the over current limit set resistor can be calculated by: where r ds(on) has to choose the maximum over the tem- perature for the selected mosfet. overall, the profile ofcurrent limit operation is shown in figure 17. figure 17 - profile of operation switching frequency versus output current. (a). normal operation.(b). current limit mode. figure 18 - operation waveforms during normal and current limit mode. d i pk_pk(lim) = (v in -v o(nom) ) 3 v o(nom) (v in 3 f s(nom) 3 l) i out(lim) = i set + d i pk_pk(lim) 2 r set = i set 3 r ds(on) 20 m a r set = (i out(lim) - d i pk_pk(lim) /2) 3 r ds(on) /20 m a ---(3) i o(max) i o(lim) switching frequency i out f s(nom) normal operation over current limit mode shutdown by uvlo i set select inductor l, frequency f s(nom) , i o(lim) set: i set = i o(lim) - d i pk_pk /2 select: r set = i set 3 r ds(on) /20 m a (v in -v o(nom) ) 3 v o(nom) v in 3 l 3 f s(nom) calculate: d i pk_pk(lim) = downloaded from: http:/// 14 rev. 1.0 3/25/04 iru3072 www.irf.com figure 20 - operation waveforms when output of buck converter is short to ground. the output uvlo senses the four feedback pin voltagesfb1,fb2,fb3,fb4. if any of the feedback voltages are below 0.4v, all four outputs will be shutdown. figure 21 - operation of pwm output and ldo when pwm output is short to ground. figure 19 - profile of switching frequency versus output current -predicted and measured. figure 18 (a) shows normal operation waveforms for a12v input 1.6v output 400khz buck regulator. during normal operation, the switching frequency is 400khz. figure 18 (b) shows the operation waveforms during cur- rent limit mode. the switching frequency is reduced and output ripple increases. figure 19 shows the profile of switching frequency versus output current. when the output current goes up and hit the over current limit, the switching frequency starts to decreases. due to the out- put voltage loop, the output voltage will keep the regula- tion except the ripple increases. as the output current keeps going up. the output voltage will start to decrease until the feedback voltage fb is under 0.4v. the output voltage under lockout takes over and turns off both high side and low side mosfet. the output voltage reduces to zero. output feedback uvlo besides the cycle-by-cycle current limit, an output feed- back uvlo is included in the iru3072 for the output short protection. the diagram is shown in figure 14. if the output is short or overload, once the voltage at the fb1 pin is below 0.4v, the output feedback uvlo com- parator will flip and turn off both high side and low side mosfets. the output of converter will decrease to zero. the operation when pwm output is in short circuit con- dition is shown in figure 20. if either pwm or ldo out- put is in short condition, it will turn off all outputs. the operation waveforms are shown in figures 21 and 22. figure 23 shows a soft-start operation when the output is short. because of current limit and output feedback uvlo, the output will be turned off and the system pro- tected. 0 50 100 150 200 250 300 350 400 450 0 2 4 6 8 10 iout (a) frequency (khz) fs(measured) fs(predicted) downloaded from: http:/// iru3072 15 rev. 1.03/25/04 www.irf.com design exampleinput voltage for buck converter: v in =12v output voltage for buck converter: v out =1.2v nominal output current from switching regulator: i out =8a output current limit is 10a.switching frequency: f s =400khz the maximum dynamic output voltage droop at 8a stepload is 150mv. ldo specification ldo input voltage: v in(ldo) =3.3v ldo output1: v out2 =2.5v @ 2a ldo output2: v out3 =1.8v @ 2a ldo output3: v out4 =1.5v @ 2a output inductor selectionthe inductor is selected based on the inductor current ripple, operation frequency and efficiency consideration. in general, a large inductor results in a small output ripple and higher efficiency but large size. a small value induc- tor causes large current ripple and poor efficiency but small size. generally, the inductor is selected based on the output current ripple. the optimum point is usually found between 20% and 50% ripple of output inductor current. suppose the ripple is selected as 40% of the total out- put current. the current ripple is calculated as: combining of above two equations, the inductance can be selected by: in this example, select inductor from panasonic so that l=1 m h. the ripple current is calculated as: figure 22 - operation of pwm output and ldo when ldo v out2 is short. figure 23 - soft-start with output is short to ground. switching frequencythe switching frequency of iru3072 can be selected by the following figure. figure 24 - switching frequency versus resistor rt. d i pk_pk /i out = 40% d i pk_pk = (12 - 1.2) 3 1.2/(1 m h 3 400khz 3 12) d i pk_pk @ 2.7a l > 1.2v 3 (12 - 1.2)/(400khz 3 12v 3 0.4 3 8a) l > 0.8 m h l > v out 3 (v in -v out )/(f s 3 v in 3 40% 3 i out ) d i pk_pk = (v in -v out ) 3 v out /(l 3 f s 3 v in ) 0 50 100 150 200 250 300 350 400 450 500 0 50 100 150 200 rt (k vv ) frequency (khz) downloaded from: http:/// 16 rev. 1.0 3/25/04 iru3072 www.irf.com d v stepload(spec) = 150mv d i stepload(max) = 8a esr < d v ripple(spec) / d i pk_pk oresr < d v stepload(spec) / d i stepload(max) output capacitor selectionthe voltage rating of the output capacitor is the same as the output voltage. typical available capacitors on the market are electrolytic, tantalum and ceramic. if electro- lytic or tantalum capacitors are employed, the criteria is normally based on the value of effective series resis-tance (esr) of total output capacitor. in most cases, the esr of the output capacitor is calculated based on the following relationship: depending on which one is the requirement. in this example: the required esr is calculated as: select three sanyo poscap 6tpb330m with 6.3v 330 m f and 40m v esr will give about 13m v , which will meet the specification.input capacitor selection input capacitor is dertermined by the voltage rating and input rms current. for this application, the input rms current is given as: the input rms current is estimated as: select two sanyo poscap -16tpb47m with 16v, 47 m f and 1.4a ripple current. a 1 m h, 1a small input inductor is enough for the input filer.power mosfet selection in general, the mosfet selection criteria depends on the maximum drain-source voltage, rms current and on resistance (r ds(on) ). for both high side and low side mosfets, a drain-source voltage rating higher thanmaximum input voltage is necessary. in the demo-board, 20v rating should be satisfied. the gate drive require- where:d v ripple(spec) is the maximum allowed voltage ripple. d i pk_pk is the current ripple. d v stepload(spec) is the maximum allowed voltage droop during the transient or step load.d i stepload(max) is the maximum step load current. ment for each mosfet is almost the same. if logic-level or 3v driver mosfet is used, some caution should be taken with devices at very low v gs to prevent undes- ired turn-on of the complementary mosfet, which re-sults a shoot-through circuit. if output inductor current ripple is neglected, the rms current of high side switch is given by: the rms current of low side switch is given as: for low side mosfet, if it is driven by 5v, a logic gate driver mosfet is preferred. for r ds(on) of the mosfet, it should be as small as possible in order to get highestefficiency. a logic driver mosfet such as irf7460 from international rectifier in a soic 8-pin package, r ds(on) =10m v , 20v drain source voltage rating and 12a i ds is selected for high side and low side mosfet. power dissipation for mosfetsthe power dissipation for mosfets typically includes conduction loss and switching losses. for high side switch, the conduction loss is estimated as: the r ds(on) has to consider the worst case. in the datasheet of irf7460:the switching loss is more difficult to calculate because of the parasitic parameters. in general, the switching loss can be estimated by the following: tr is the rising time and tf is the falling time. from iru3072 datasheet: tr=50ns and tf=50ns the total disspation for the high side switch is: for low side switch, most of the loss are conduction loss. the low side switch power dissipation is: p sw = 0.5 3 v ds 3 i out 3 (tr+tf) 3 f s p sw(hi) = 0.5 3 12v 3 8a 3 (50ns+50ns) 3 400khz p sw(hi) @ 1.92w p d(hi) = p sw(hi) +p cond(hi) @ 2w p d(lo) @ p cond(lo) = (1-d) 3 i out 3 i out 3 r ds(on)max p d(lo) @ p cond(lo) = (1-0.1) 3 8a 3 8a 3 14m v p d(lo) @ p cond(lo) = 0.81w p cond(hi) = d 3 i out 3 i out 3 r ds(on)max r ds(on)max = 14m v @ vgs = 4.5v p cond(hi) = 0.1 3 8a 3 8a 3 14m v @ 0.09w esr < 150mv/8a = 18.75m v i in(rms) = i out 3 d 3 (1-d) d = v out /v in = 1.2v/12v @ 0.1 i in(rms) = 8a 3 0.1 3 (1-0.1) @ 2.4a i rms(hi) = 1-d 3 i out = 1-0.1 3 8a = 7.6a d = v out /v in = 0.1 i rms(hi) = d 3 i out = 0.1 3 8a = 2.53a downloaded from: http:/// iru3072 17 rev. 1.03/25/04 www.irf.com i o(lim) = 10a d i pk_pk = (12-1.2) 3 1.2/(1 m h 3 400khz 3 12) d i pk_pk @ 2.7a i set = i o(lim) - d i pk_pk /2 = 10a-2.7a/2 @ 8.7a r set = i set 3 r ds(on) /20 m a r set = 8.7a 3 14m v /20 m a = 6.09k v f o = 40khz http://www.irf.com/technical-info/appnotes.htm t j = t a +p d 3 r u ja = 35+2 3 50 = 135 8 c < 150 8 c c ss = 20 m a 3 t start = 20 m a 3 5ms = 0.1 m f t j = t a +p d 3 r u ja = 35+0.81 3 50 = 76 8 c < 150 8 c rc1= 2 p3 f o 3 l 3 v osc 3 v out (esr 3 v in 3 g m 3 v ref ) cc1 = (l 3 c out )/0.75/rc1 cc1 = (1 m h 3 450 m f)/0.75/3.3k = 10nf select c9=cc1=15nf for low side mosfet irf7460, with 4.5v gate volt-age and maximum r ds(on) of 14m v , then: select r7=r set =6.8k v (4) compensation design figure 25 - type ii compensator. for electrolytic capacitor, the frequency caused byesr is typically at a few khz range. a type ii com- pensator is a good option. the detailed description is shown in application note an-1043 from: select the zero crossover frequency to be 1/10 of switching frequency that is 40khz: the compensation resistor can be calculated as: where v osc is the oscillator peak to peak voltage and gm is the transconductance of the error ampli-fier. from the datasheet we get v osc =1.25v and g m =1000 m mho. the calculated compensation resis- tor is:the compensator capacitor is given as: rc1=2 p3 40 3 1 3 1.25 3 1.2/(13 3 12 3 1000 3 0.8) rc1=2.98kselect r8=rc1=3.3k g m rf1 rf2 v out v fb 1v comp cc1 rc1 cc2 (optional) iru3072 error amp t j = t a +p d 3 r u ja where:t j is the junction temperature. t a is the ambient temperature. p d is the power dissipation. r u ja is the junction-to-ambient thermal resistance with mosfet on 1" square pcb board and is fromthe data sheet. estimated temperature rise for mosfetthe estimated junction temperature of the mosfet is given by: for mosfet irf7460 with soic 8-pin package, r u ja =50 8 c/w. assume ambient temperature is t a =35 8 c. for high side mosfet, the junction temperature is givenas: for low side mosfet irf7460, the maximum junction temperature can be calculated as: the maximum junction temperature of both mosfets is below the maximum rating of 150 8 c. controller parameter calculation(1) frequency selection from figure 23, the frequency setting resistor canbe chosen to be rt=47k v , which gives us approxi- mately 400khz frequency. (2) soft-start capacitor soft-start capacitor for pwm secton is selected fromequation (1). select start up time t start =5ms: select c11=c ss =0.1 m f (3) over current limit setting the over current limit resistor can be calculated basedon figure 17. the output current limit is set by: the current ripple during nomral operation (400khz) is given by: the over current setting i set is: the over current setting resistor: downloaded from: http:/// 18 rev. 1.0 3/25/04 iru3072 www.irf.com t j = t a +p d 3 (r u jc +r u cs+ r u sa ) t j should be < t j(max) @ 150 8 c where:t j = the estimated junction temperature. t a = the ambient temperature. p d = the power disspation. r u jc = the thermal resistance from junction to case. r u cs = the thermal resistance from case to heat sink. r u sa = the thermal resistance from heat sink to am- bient. the required thermal resistance of heat sink should bein this example, the mosfet is mounted in the copper area more than 1 square inch. the estimated junction temperaure is: where r u ja is the thermal resistance from junction to ambient with pcb mounted.for irlr2703s, r u ja =50 8 c/w, assume: the thermal managment can meet the requirement.vccldo selection for ldo, the ldo controller supply voltage has to sat- isfy the following:for this example, v gs(th)min of mosfet irlr2703s, is 1v. then:ldo feedback resistor selection the output of ldo is determined by: for 2.5v output, if r b =1k then: select rt=2.15k ldo soft-start capacitorthe soft-start capacitor can be estimated from equation (1). select start up time as 2ms: (optional) an additional capacitor cc2 can beadopted, where: (5) feedback resistor the output of pwm is determined by:where v ref =0.8v r t is the top feedback resistor and r b is bottom feedback resistor.for 1.2v output, r t =499 v , r b =1k. ldo regulator component selectionand ldo power mosfet selection the first step in selecting the power mosfet for the linear regulator is to select its maximum r ds(on) based on the input to output dropout voltage and maximumload current. for v out2 =2.5v, v in(ldo) =3.3v and i out2 =2a: note that the mosfet?s r ds(on) increases with tem- perature, the calculated r ds(on) has to be divided by the r ds(on) temperature coefficienct (about 1.5) in order to get typical r ds(on). irlr2703s from internation rectifier with d2 package,30v, v ds logic drive and 65m v is good enough to meet the requirement.to select the heat sink for the ldo mosfet, the first step is to calculate the maximum power dissipation of the device: the junction temperature of mosfet can be estimated by the following formula: cc2 @ 1/( p3 rc1 3 f s ) @ 220pf v out = v ref 3 (r t +r b )/r b orr t = (v out /v ref -1) 3 r b r ds(on)max = (v in(ldo) -v out2 )/i out2 r ds(on)max = (3.3v-2.5v)/2.0a = 0.4 v p d = (v in(ldo) -v out ) 3 i out p d = (3.3v-2.5v) 3 2a = 1.4w r u sa <(t j -t a )/p d -r u jc -r u cs t j =t a +p d 3 r u ja t a = 35 8 c t j = 35+1.5w 3 50 8 c/w = 110 8 c < 150 8 c v cc(ldo) > v ldo(out)max +v gs(th)min +2v be where:v ldo(out)max is the maximum output voltage v gs(th)min is the minimum ldo mosfet gate thresh- old voltagev be is the diode drop, approximately 0.6v v cc(ldo) > 2.5v+1v+2 3 0.6v = 4.7v select v ccldo =12v for proper power sequence where:v ref =0.8v r t is the top feedback resistor and r b is bottom feedback resistor. v out = v ref 3 (r t +r b )/r b r t = (v out /v ref -1) 3 r b = (2.5/0.8-1) 3 1k = 2.12k c ss(ldo) = 20 m a 3 t start = 20 m a 3 2ms = 0.04 m f select c12=c ss(ldo) =33nf downloaded from: http:/// iru3072 19 rev. 1.03/25/04 www.irf.com layout considerationthe layout is very important when designing high fre- quency switching converters. layout will affect noise pickup and can cause a good design to perform with less than expected results. start to place the power components, make all the con- nection in the top layer with wide, copper filled areas. the inductor, output capacitor and the mosfet should be close to each other as possible. this helps to reduce the emi radiated by the power traces due to the high switching currents through them. place input capacitor directly to the drain of the high-side mosfet, to reducethe esr replace the single input capacitor with two par- allel units. the feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the ic. in multilayer pcb use one layer as power ground plane and have a control cir- cuit ground (analog ground), to which all signals are ref- erenced. the goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. these two grounds must be connected together on the pc board layout at a single point. figure 26 - transient response with 8a load. figure 27 - transient response (zoomed). figure 28 - transient response (zoomed). application experimental waveforms for application circuit in figures 1 and 3 downloaded from: http:/// 20 rev. 1.0 3/25/04 iru3072 www.irf.com figure 29 - iru3072 typical application with one bus input voltage v cc =v bus =5v and 3.3v for ldo. figure 30 - iru3072 typical application with 5v bus input and 12v for the driver (charge pump is saved). typical applications iru3072 u1 vcc vc hdrv ldrv fb1 gnd comp ss1 v out1 0.8v rt ocset pgnd drv4 fb4 drv3 fb3 drv2 fb2 v sen33 / sdb ssldo c716tpb47m 47uf, 16v c810uf c123x 6tpb330m 6.3v, 330uf, 40m v 1uh l1 q4irf7460 q5irf7460 r7 vccldo v in =5v 12v c11uf 6.8k c31uf 3.3v v out2 2.5v v out3 1.8v v out4 1.5v q1 irlr2703 q2 c2 q3 c4 c9 c130.1uf c14 33nf c11 2.15k r21k 1.24k r41k 866 r6 1k 6.8k 46.4k c10 100pf r1 r3 r5 r9 r8 l2 1uh 10nf iru3072 u1 vcc vc hdrv ldrv fb1 gnd comp ss1 v out1 1.2v @ 8a rt ocset pgnd drv4 fb4 drv3 fb3 drv2 fb2 v sen33 / sdb ssldo c716tpb47m 47uf, 16v c810uf c123x 6tpb330m 6.3v, 330uf, 40m v l2 1uh l1 q4irf7460 q5irf7460 r7 vccldo v in =5v c51uf c11uf c60.1uf 6.8k r11 1k r10 3.3v v out2 2.5v v out3 1.8v v out4 1.5v q1 irlr2703 q2 c2 q3 c4 c9 c130.1uf c14 33nf c11 2.15k r21k 1.24k r41k 866 r6 1k 6.8k 46.4k c10 100pf r1 r3 r5 r9 r8 1k 1uh 10nf downloaded from: http:/// iru3072 21 rev. 1.03/25/04 www.irf.com typical applications figure 31 - iru3072 typical application with ceramic capacitor output. figure 32 - iru3072 typical application with one bus input voltage v cc =v bus =12v and 3.3v for ldo. iru3072 u1 vcc vc hdrv ldrv fb1 gnd comp ss1 v out1 1.2v @ 5a rt ocset pgnd drv4 fb4 drv3 fb3 drv2 fb2 v sen33 / sdb ssldo 3.3v v out2 2.5v v out3 1.8v v out4 1.5v q1 irlr2703 q2 c2 q3 c4 c9 c130.1uf c14 33nf c11 c747uf,16v c8 10uf c122x 47uf ceramic 1uh 1uh q4irf7460 q5irf7460 2.15k r21k 1.24k r41k 866 r6 1k 10k 47k r7 vccldo v in =12v c51uf c11uf c60.1uf 4.7k c10 82pf +5v c31uf r1 r3 r5 r9 r8 l2 l1 d1 d2 r10 62k r114.64k c15 220pf 3.3nf r12 124k iru3072 u1 vcc vc hdrv ldrv fb1 gnd comp ss1 v out1 1.2v rt ocset pgnd drv4 fb4 drv3 fb3 drv2 fb2 v sen33 / sdb ssldo c716tpb47m 47uf, 16v c810uf c123x 6tpb330m 6.3v, 330uf, 40m v l2 1uh l1 q4irf7460 q5irf7460 r7 vccldo v in =12v c51uf c11uf c60.1uf 6.8k r11 1k r10 3.3v v out2 2.5v v out3 1.8v v out4 1.5v q1 irlr2703 q2 c2 q3 c4 c9 c130.1uf c14 33nf c11 2.15k r21k 1.24k r41k 866 r6 1k 3.3k 47k c10 220pf r1 r3 r5 r9 r8 1k 1uh 200 v r12 15nf downloaded from: http:/// 22 rev. 1.0 3/25/04 iru3072 www.irf.com typical application figure 33 - iru3072 typical application with one bus input voltage v cc =v bus =12v to generate all ldo output. iru3072 u1 vcc vc hdrv ldrv fb1 gnd comp ss1 v out1 3.3v rt ocset pgnd drv4 fb4 drv3 fb3 drv2 fb2 v sen33 / sdb ssldo c716tpb47m 47uf, 16v c810uf c123x 6tpb330m 6.3v, 330uf, 40m v l2 l1 q4irf7460 q5irf7460 r7 vccldo v in =12v c51uf c11uf c60.1uf 6.8k r11 1k r10 3.3v v out2 2.5v v out3 1.8v v out4 1.5v q1 irlr2703 q2 c2 q3 c4 c9 c130.1uf c14 33nf c11 2.15k r21k 1.24k r41k 866 r6 1k 3.3k 47k c10 220pf r1 r3 r5 r9 r8 3.125k 1uh 200 v r12 1k r13 1uh 15nf downloaded from: http:/// iru3072 23 rev. 1.03/25/04 www.irf.com (h) mlpq package 20-pin symbol desig a a1a3 b d d2 e e2 el r min 0.800.00 0.18 2.00 2.00 0.45 0.09 nom 0.900.02 0.23 2.15 2.15 0.55 --- 4.00 bsc max 1.000.05 0.30 2.25 2.25 0.65 --- 4.00 bsc0.50 bsc 20-pin 4x4 note 1: details of pin #1 are optional, but must be located within the zone indicated.the identifier may be molded, or marked features. 0.20 ref note: all measurements are in millimeters. a3 a1 a e2 e d/2 d2 e l b exposed pad bottom view top view pin number 1 side view e/2 d pin 1 mark area (see note1) r downloaded from: http:/// 24 rev. 1.0 3/25/04 iru3072 www.irf.com pkg desig h package description mlpq 4x4 parts per tube tbd parts per reel tbd package shipment method pin count 20 t & r orientation fig a ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information data and specifications subject to change without notice. 02/01 feed direction figure a this product has been designed and qualified for the industrial market. downloaded from: http:/// |
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